This invention relates to semiconductor structures and more particularly to dynamic random access memory structures.
As is known in the art, for the commercial success of future generations of semiconductor memories, it will be essential to minimize die sizes and at the same time increase performance characteristics. One type of semiconductor memory is a dynamic random access memory (DRAM). In one such DRAM, an array of memory cells is provided. Each one of the memory cells incudes a transistor coupled to a storage capacitor. In a deep trench DRAM cell, the capacitor is formed in a deep trench which passes vertically into the surface of the semiconductor thereby reducing size as compare to a stack capacitor cell. Still, as noted above, for commercial success cell sizes must continue to be reduced.